Lower bounds on power-dissipation for DSP algorithms

The author presents a fundamental mathematical basis for determining the lower bounds on power dissipation in digital signal processing (DSP) algorithms. This basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Different architectures implementing a given algorithm are equivalent to different communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. The proposed framework is employed to determine the lower bounds for simple digital filters. Furthermore, lower bounds on the power dissipation achievable via adiabatic logic are also presented, thus demonstrating the versatility of the proposed approach