Title :
Energy recovery for the design of high-speed, low-power static RAMs
Author :
Tzartzanis, Nestoras ; Athas, William C.
Author_Institution :
Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
Abstract :
We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-recovery SRAM was evaluated through SPICE simulations and compared with a standard design. Simulation results of a 256 × 256 memory configuration indicate that, for successive write operations, energy saving for the different SRAM functions vary from 59% to 76% at 200 MHz operating frequency compared to the conventional design.
Keywords :
SRAM chips; 200 MHz; 256/spl times/256 memory configuration; CMOS VLSI; SPICE simulations; clock driver circuit; energy dissipation models; energy recovery; energy saving; high-speed low-power SRAM design; power dissipation; write operations; Capacitance; Clocks; Driver circuits; Frequency synchronization; Random access memory; Read-write memory; Resonance; Signal generators; Voltage;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.542730
