DocumentCode
1713178
Title
A novel current-mode Winner-Take-All topology
Author
Moro-Frias, D. ; Sanz-Pascual, M.T. ; de la Cruz Blas, C.A.
Author_Institution
Electron. Dept., INAOE, Puebla, Mexico
fYear
2011
Firstpage
134
Lastpage
137
Abstract
In this paper a novel Winner-Take-All (WTA) topology is presented which shows good trade-off between resolution and resolution speed, at the cost of some increase in power consumption. The proposed WTA is compared with other current-mode WTAs found in literature based on the same operation principle. All the topologies were designed in a 0.13 μm CMOS process and characterized in terms of resolution, resolution speed, supply voltage, compactness and power consumption. The novel WTA shows the highest resolution speed and the best trade-off between performance parameters.
Keywords
CMOS integrated circuits; current-mode circuits; network topology; CMOS process; current-mode winner-take-all topology; power consumption; resolution speed; size 0.13 mum; supply voltage; Current measurement; Integrated circuits; Neural networks; Power demand; Topology; Transistors; Current-Mode Analog Design; Winner-Take-All Circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design (ECCTD), 2011 20th European Conference on
Conference_Location
Linkoping
Print_ISBN
978-1-4577-0617-2
Electronic_ISBN
978-1-4577-0616-5
Type
conf
DOI
10.1109/ECCTD.2011.6043295
Filename
6043295
Link To Document