• DocumentCode
    1713309
  • Title

    Solder joint reliability model vath modified Darveaux´s equations for the micro smd wafer level-chip scale package family

  • Author

    Zhang, L. ; Sitaraman, R. ; Patwardhan, V. ; Nguyen, L. ; Kelka, N.

  • Author_Institution
    National Semiconductor Corporation
  • fYear
    2003
  • Firstpage
    572
  • Lastpage
    577
  • Keywords
    Chip scale packaging; Electronic packaging thermal management; Electronics packaging; Equations; Fatigue; Semiconductor device modeling; Semiconductor device packaging; Soldering; Testing; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2003. Proceedings. 53rd
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-7791-5
  • Type

    conf

  • DOI
    10.1109/ECTC.2003.1216338
  • Filename
    1216338
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1713309