Non-idealities in linear CDR phase detectors

The effects of circuit non-idealities in a “Hogge ” -type phase detector are examined. Using a behavioral model for each circuit block, it is shown that various circuit non-idealities introduce static phase offset in the phase detector, reduce the monotonic range of its transfer characteristics and eventually degrade the capture range and jitter tolerance of the clock and data recovery (CDR) loop. Lower bounds on the bandwidths of the various blocks in the CDR are also established in order to avoid variations of the transfer characteristics.