Batch fabrication of through-wafer vias in CMOS wafers for 3-D packaging applications

Author

Rasmussen, F.E. ; Hesche, M. ; Hansen, O.

Author_Institution

Technical University of Denmark

fYear

2003

Firstpage

634

Lastpage

639

Keywords

CMOS process; CMOS technology; Circuits; Etching; Fabrication; Metallization; Packaging; Plasma temperature; Silicon; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2003. Proceedings. 53rd

ISSN

0569-5503

Print_ISBN

0-7803-7791-5

Type

DOI

10.1109/ECTC.2003.1216348

Filename

1216348

Link To Document