A 12 GB/s 3-GHz input bandwidth track-and-hold amplifier in 65 nm CMOS with 48-dB spur-free dynamic range

A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The cascode topology with inductive peaking technique is employed to enhance voltage headroom and bandwidth. The input parasitic capacitance of the output buffer is designed as the hold-mode element to further reduce chip size. The dc supply voltage is 1.8 V with a total power consumption of 197 mW. When the input frequency is 2.42 GHz with an input voltage swing of 0.5 Vpp and the sampling rate is 12 GB/s, this work demonstrates a spur-free dynamic range of 48 dB, a total harmonic distortion of -45.8 dB, and an input bandwidth of 3 GHz.