DocumentCode
1714097
Title
Power delivery design and analysis on a network processor board
Author
Cui, Wei ; Aspnes, Brian ; Parmar, Prashant ; Suryakumar, Mahadevan
Author_Institution
Intel Corp., Hillsboro, OR, USA
Volume
1
fYear
2004
Firstpage
231
Abstract
The power delivery design and analysis method is presented on a network processor board design. The design is accomplished by placing a large number of capacitors in the pin field using a via sharing pattern, and adding embedded capacitance with extra power planes to optimize the power delivery network. The innovative design reduced the voltage droop and resistive loss. Measurements were made and the design was validated. A full-scale analysis of power delivery network was performed with rigorous model extraction. The simulation results correlated well with the measurements.
Keywords
capacitance; circuit optimisation; electromagnetic compatibility; printed circuit design; EMC; capacitors; embedded capacitance; model extraction; network processor board; optimization; pin field; power delivery analysis; power delivery design; via sharing pattern; Capacitors; Circuit simulation; Current supplies; High speed integrated circuits; Integrated circuit measurements; Performance analysis; Pins; Process design; Rails; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electromagnetic Compatibility, 2004. EMC 2004. 2004 InternationalSymposium on
Print_ISBN
0-7803-8443-1
Type
conf
DOI
10.1109/ISEMC.2004.1350031
Filename
1350031
Link To Document