Title :
OTA based neural network architectures with on-chip tuning of synapses
Author :
Ghosh, Joydeep ; Lacour, Patrick ; Jackson, Spence
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
We propose and analyze analog VLSI implementations of neural networks in which both the neural cells and the synapses are realized using Operational Transconductance Amplifiers (OTAs). These circuits have inherent advantages of immunity to noise, very high input/output impedances, differential architecture with automatic inversion, and density. An efficient on-chip technique for weight adaptation and for adjusting the gain of OTA-based neurons is proposed. Power and area requirements are obtained. We consider OTAs as a basic building block for efficiently constructing several types of artificial neural networks including Hopfield networks, Boltzmann machines and cellular networks. Circuit simulations using MTIME show that small Hopfield memories converge in about a μsec
Keywords :
Boltzmann machines; Hopfield neural nets; VLSI; circuit analysis computing; linear integrated circuits; neural chips; operational amplifiers; Boltzmann machines; Hopfield networks; MTIME; OTA-based neurons; analog VLSI implementation; artificial neural networks; automatic inversion; cellular networks; circuit simulation; differential architecture; input/output impedances; neural cells; neural network architectures; noise immunity; on-chip synapse tuning; operational transconductance amplifiers; small Hopfield memories; weight adaptation; Artificial neural networks; Circuit noise; Circuit optimization; Impedance; Network-on-a-chip; Neural networks; Neurons; Operational amplifiers; Transconductance; Very large scale integration;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282659
