A VLSI architecture of an inverse discrete cosine transform

The inverse discrete cosine transform (IDCT) is an important function in HDTV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the sequence of input coefficients and the output data, the rows and columns of the transform matrix can be reordered to build modular regularity which is suitable for VLSI implementation. Based on this technique, an architecture using only seven constant multipliers and only one 1 dimensional IDCT processor is presented