Loop Scheduling for Transport Triggered Architecture Processors

Compilation of programs for highly parallel processors requires efficient scheduling of parallel resources. The innermost loops should achieve the highest throughput possible with the available resources. In this paper, a scheduling method for transport triggered architecture (TTA) processors is proposed. Especially, the developed method is capable of scheduling loops with software pipelining. The scheduler maps graph presentation of the program to parallel computing resources. The resource conflicts are resolved in an iterative manner with graph node adjustments and rescheduling. With the proposed method, the achieved performance is comparable to the performance of manual scheduling. Thus, the proposed method gives a strong argument for applying highly parallel programmable TTA processors in DSP applications