Title :
Two-layer wiring with pin preassignments is easier if the power supply nets are already generated
Author :
Molitor, Paul ; Sparmann, Uwe ; Wagner, Dorothea
Author_Institution :
Dept. of Comput. Sci., Saarlandes Univ., Saarbrucken, Germany
Abstract :
We examine the constrained via minimization problem with pin preassignments (CVMPP) which arises in connection with hierarchical physical synthesis. Let A be a circuit composed of subcircuits B, C, D,.... Assume that the placement and routing phase together with the 2-layer wiring of the subcircuits, and the placement and routing phase without the 2-layer wiring of A are completed. CVMPP is the problem of finding a 2-layer wiring δA of A which is induced by the 2-layer wirings of the subcircuits and which contains a minimal amount of vias on this condition. First, we show that CVMPP is NP-hard. In the case that the wiring of the power supply nets has already been generated we present a polynomial time algorithm solving CVMPP
Keywords :
VLSI; circuit layout; computational complexity; integrated circuit technology; minimisation; network routing; NP-hard problem; constrained via minimization problem; hierarchical physical synthesis; pin preassignments; placement; polynomial time algorithm; power supply nets; routing; two-layer wiring; Circuit synthesis; Minimization; Physical layer; Pins; Polynomials; Power generation; Power supplies; Routing; Wire; Wiring;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282674
