Design considerations on CMOS limiting amplifiers for wearable biomedical systems

Author

Ramos, J. ; Ausín, J.L. ; Duque-Carrillo, J.F. ; Torelli, G.

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. of Extremadura, Badajoz, Spain

fYear

2011

Firstpage

294

Lastpage

297

Abstract

This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process and mismatch variations was designed in 0.35-μm CMOS technology to operate over a dc-to-20-MHz bandwidth. The proposed limiting amplifier draws 280 μA from a 2-V supply and achieves a voltage gain of 75 dB.

Keywords

CMOS integrated circuits; Monte Carlo methods; amplifiers; biomedical engineering; limiters; CMOS limiting amplifiers; Monte Carlo simulation; current 280 muA; device level properties; gain 75 dB; gain bandwidth product; low voltage gain cell topologies; mismatches; power-efficient logarithmic amplifiers; sensitivity; voltage 2 V; wearable biomedical systems; Accuracy; CMOS integrated circuits; Gain; Limiting; Power demand; Sensitivity; Transistors; CMOS analog integrated circuits; biomedical electronics; limiting amplifiers; logarithmic amplifiers; mismatch;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design (ECCTD), 2011 20th European Conference on

Conference_Location

Linkoping

Print_ISBN

978-1-4577-0617-2

Electronic_ISBN

978-1-4577-0616-5

Type

conf

DOI

10.1109/ECCTD.2011.6043344

Filename

6043344