Design And Verification of a VHDL Model of a Floating-Point Unit for a RISC Microprocessor

In modern systems-on-chip (SoCs) a widely used technique to reduce design and testing time consists of building up the whole system by connecting together simpler, IP-reusable blocks. Each block implements a specific functionality and is designed and tested separately from the other components of the system. This allows a local verification procedure, with significant advantages in terms of time and cost. In this paper is described how we applied the philosophy mentioned above to the design of a synthesizable VHDL model of a parametric 32-bit floating-point unit, and how its verification has been carried on using many different techniques that combined together ensure a reduction of testing time