Title :
IDDQ detection of CMOS bridging faults by stuck-at fault tests
Author :
Hwang, S. ; Rajsuman, R. ; Davidson, Scott
Author_Institution :
Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
Many of the physical defects in CMOS circuits such as bridging and transistor stuck-on faults are not guaranteed to be detected by logic testing. In this paper, we examine the detection efficiency of stuck-at tests in covering all possible bridging faults in IDDQ environment. We generate stuck-at fault test vectors for combinational and sequential benchmark circuits using standard ATPG programs. The circuits are simulated with these vectors and power supply current was monitored for bridging faults. A high current state in a faulty circuit is considered as an indicator of fault detection. The test results are given in terms of intra-transistor and gate-level bridging fault coverage. Our results show that stuck-at test vectors can be used very efficiently for IDDQ testing of bridging faults, and extra effort to generate specialized test vectors may be unnecessary
Keywords :
CMOS integrated circuits; circuit analysis computing; combinatorial circuits; integrated logic circuits; logic testing; sequential circuits; CMOS bridging faults; IDDQ detection; circuit simulation; combinational benchmark circuits; detection efficiency; gate-level bridging fault coverage; high current state; intra-transistor bridging fault coverage; physical defects; power supply current; sequential benchmark circuits; standard ATPG programs; stuck-at fault tests; Automatic test pattern generation; Benchmark testing; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Logic testing; Sequential analysis;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282681
