Title :
Testable realizations of CMOS combinational circuits for voltage and current testing
Author :
Biswas, K. ; Rai, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
Abstract :
This paper studies the potential invalidation of tests for detecting stuck-on faults derived by neglecting circuit delays. A design for testability (DFT) technique for detecting stuck-open and stuck-on faults using voltage testing in NAND/NAND (NOR/NOR) realizations derived from irredundant sum (product) of prime implicants (implicates) is presented. The proposed design has the advantage over previous designs in that, both single stuck-open and stuck-on faults are detected by tests that are valid in the presence of input as well as circuit delays. A new current testing technique for detecting stuck-open faults in the same class of circuits is also proposed. The advantage of this method over voltage testing is, in this technique stuck-open faults can be detected even if the NAND/NAND realization is part of a larger multilevel circuit
Keywords :
CMOS integrated circuits; combinatorial circuits; delays; design for testability; electric current measurement; integrated circuit testing; integrated logic circuits; logic testing; voltage measurement; CMOS combinational circuits; NAND/NAND realization; NOR/NOR realization; circuit delays; current testing; design for testability; fault detection; multilevel circuit; stuck-on faults; stuck-open faults; voltage testing; Circuit faults; Circuit testing; Combinational circuits; Delay; Design for testability; Electrical fault detection; Fault detection; Inverters; Logic testing; Voltage;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282684
