A 135–160 GHz balanced frequency doubler in 45 nm CMOS with 3.5 dBm peak power

A 135-160 GHz active doubler has been developed in 45 nm CMOS SOI. Careful optimization is done on the transistor size, layout and transmission-lines in order to result in the best performance. The doubler shows a measured peak power of +3.5 dBm at 150 GHz and > 2 dBm at 140-160 GHz, at a bias voltage of 1 V. These were achieved at an input power of 7-8 dBm at 70-80 GHz, resulting in a conversion gain of -4 to -5 dBm. To our knowledge, these are the best results achieved for a D-band doubler in SiGe or CMOS, and shows that advanced CMOS technology can be used to generate wideband power above 100 GHz.