DocumentCode :
1714816
Title :
GLOVE: a graph-based layout verifier
Author :
Bamji, Cyrus S. ; Allen, Jonathan
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
fYear :
1994
Firstpage :
215
Lastpage :
220
Abstract :
A technique for the design rule verification of layouts composed of library cells is presented. Instead of directly manipulating mask geometries, DRC correctness is tied to a set of user defined patterns of allowed cell interactions called templates. Design rule verification is achieved by covering the layout with these templates. Both layouts and templates are defined in terms of graphs and all operations are performed in the graph domain. The verification procedure is incremental and because the number of cell instances is much smaller than the number of mask geometries it is much faster than techniques that directly manipulate mask geometries
Keywords :
VLSI; circuit layout CAD; computational complexity; graph theory; integrated circuit technology; DRC correctness; GLOVE; VLSI layout; design rule verification; graph-based layout verifier; graphs; library cells; templates; user defined patterns; Ear; Fabrication; Fault diagnosis; Geometry; Hardware; Libraries; Parallel processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
ISSN :
1063-9667
Print_ISBN :
0-8186-4990-9
Type :
conf
DOI :
10.1109/ICVD.1994.282688
Filename :
282688
Link To Document :
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