A sea-of-gates style FPGA placement algorithm

The placement objectives for field programmable gate arrays (FPGAs) is to achieve 100% routability within the architectural constraints. We present a hierarchical placement approach for a sea-of-gates style FPGA. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90% reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool) developed specifically for this architecture