DocumentCode
1714881
Title
Formal Modelling of Multiclocked SoC Systems
Author
Westerlund, Tomi ; Plosila, Juha
Author_Institution
Turku Centre for Comput. Sci., Turku
fYear
2006
Firstpage
1
Lastpage
4
Abstract
We introduce a formal, time aware model for multiclocked SoC systems using the action systems formalism spiced with timing information. The multiclocked SoC model by itself guarantees the correct operation of the correct synchronous operation, and the data integrity during communication is ensured using a procedure based communication scheme and the prioritised composition that disables computation during communication activities.
Keywords
data integrity; integrated circuit modelling; system-on-chip; timing; action systems formalism; data integrity; formal modelling; multiclocked SoC systems; synchronous operation; time aware model; Clocks; Command languages; Computer science; Delay systems; Design methodology; Information technology; Signal design; Signal synthesis; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2006. International Symposium on
Conference_Location
Tampere
Print_ISBN
1-4244-0621-8
Electronic_ISBN
1-4244-0622-6
Type
conf
DOI
10.1109/ISSOC.2006.321987
Filename
4116475
Link To Document