Adaptive sensing and image processing with a general-purpose pixel-parallel sensor/processor array integrated circuit

Author

Dudek, Piotr

Author_Institution

Univ. of Manchester, Manchester

fYear

2006

Firstpage

1

Lastpage

6

Abstract

In this paper, a pixel-parallel image sensor/processor architecture with a fine-grain massively parallel SIMD analogue processor array is overviewed and the latest VLSI implementation, SCAMPS vision chip, comprising 128 times 128 array, fabricated in a 0.35mum CMOS technology, is presented. Examples of real-time image-processing executed on the chip are shown. Sensor-level data reduction, wide dynamic range and adaptive sensing algorithms, enabled by the sensor-processor integration, are discussed.

Keywords

CMOS integrated circuits; image processing; image sensors; parallel processing; CMOS technology; SCAMPS vision chip; adaptive sensing; image processing; parallel SIMD analogue processor array; pixel-parallel image sensor/processor architecture; sensor-level data reduction; Adaptive arrays; CMOS image sensors; CMOS process; CMOS technology; Image processing; Image sensors; Integrated circuit technology; Pixel; Sensor arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architecture for Machine Perception and Sensing, 2006. CAMP 2006. International Workshop on

Conference_Location

Montreal, Que.

Print_ISBN

978-1-4244-0685-2

Electronic_ISBN

978-1-4244-0686-9

Type

conf

DOI

10.1109/CAMP.2007.4350340

Filename

4350340