Title :
Layout influenced factorization of Boolean functions
Author :
Jaekel, Arunita ; Bandyopadhyay, S. ; Sengupta, A.
Author_Institution :
Sch. of Comput. Sci., Windsor Univ., Ont., Canada
Abstract :
Traditional approaches to designing VLSI circuits for a given Boolean function usually treat logic minimization and layout generation as two separate subproblems which are solved independently of each other. However, actual layout considerations such as transistor placement and the routing strategy are also important factors in determining the cost of a combinational circuit. Our approach tries to factorize Boolean functions in such a way that the corresponding functional cell layout area is minimized
Keywords :
Boolean functions; CMOS integrated circuits; VLSI; circuit layout; combinatorial circuits; graph theory; integrated logic circuits; logic design; minimisation of switching nets; network routing; Boolean functions; VLSI circuit design; combinational circuit; factorization; functional cell layout area; graph model; layout generation; logic minimization; routing strategy; static CMOS technology; transistor placement; Boolean functions; CMOS technology; Computer science; Costs; Electronic mail; Integrated circuit interconnections; Logic circuits; Logic design; Routing; Very large scale integration;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282696
