On determining symmetries in inputs of logic circuits

We propose a method for computing maximal sets of symmetric inputs in large circuits, using a test generation procedure for single stuck-at faults. The method is enhanced by heuristics that can be used to identify non-symmetric inputs, and reduce the number of inputs for which test generation has to be carried out. We show the relevance of the problem to input matching for design diagnosis and for technology mapping, and show that the input patterns produced by one of the heuristics can be used for input matching as well. Experimental results demonstrate the effectiveness of the proposed procedures. We also introduce an extended definition of input symmetry that helps in effectively solving the design diagnosis and technology mapping problems