Energy efficient programmable computation

Author

Chandrakasan, Anantha P. ; Srivastava, Mani B. ; Brodersen, Robert W.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1994

Firstpage

261

Lastpage

264

Abstract

This paper describes techniques for energy efficient implementation of programmable computation. Two key approaches described here are extended voltage scaling and predictive statistical system shutdown. Results indicate that a large reduction in power consumption can be achieved over current day solutions without loss in system performance

Keywords

microprocessor chips; parallel architectures; power consumption; DSP computation; energy efficient implementation; extended voltage scaling; general purpose computation; multiple processors; parallelism; power consumption reduction; predictive statistical system shutdown; programmable computation; Computer networks; Concurrent computing; Digital signal processing; Energy consumption; Energy efficiency; Hardware; Parallel processing; Throughput; Voltage; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Conference_Location

Calcutta

ISSN

1063-9667

Print_ISBN

0-8186-4990-9

Type

conf

DOI

10.1109/ICVD.1994.282698

Filename

282698

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1715061