Title :
Development of High-resolution Digital Vision Chip Based on CFPE Architecture
Author :
Yamamoto, K. ; Kubozono, M. ; Ishii, I.
Author_Institution :
Hiroshima Univ., Hiroshima
Abstract :
In this paper, we describe VLSI implementation using a new vision chip architecture that enables various visual processings on the same architecture and combines high speed and the high accumulation. A 64 x 64 pixel prototype vision chip and its evaluation results are shown. The chip is integrated on a 3.6 mm x 3.9 mm chip using a 0.35 mum CMOS DLP/TLM process; the pixel size is 33.0 mum x 33.0 mum. The maximum current consumption is approximately 500 mA.
Keywords :
CMOS digital integrated circuits; VLSI; 3.6 mm x 3.9 mm chip; 33.0 mum x 33.0 mum; 64 x 64 pixel prototype vision chip; CFPE architecture; CMOS DLP/TLM process; VLSI implementation; high-resolution digital vision chip; size 0.35 mum; Algorithm design and analysis; CMOS process; Computer architecture; Image processing; Machine vision; Pixel; Prototypes; Real time systems; Robot control; Very large scale integration;
Conference_Titel :
Computer Architecture for Machine Perception and Sensing, 2006. CAMP 2006. International Workshop on
Conference_Location :
Montreal, Que.
Print_ISBN :
978-1-4244-0685-2
Electronic_ISBN :
978-1-4244-0686-9
DOI :
10.1109/CAMP.2007.4350344
