Title :
Power constraint scheduling of tests
Author :
Chou, Richard M. ; Saluja, Kewal K. ; Agrawal, Vishwani D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Abstract :
This paper presents motivation for considering the power constraint in testing and gives a model-based formulation of the new test scheduling problem. Optimum test scheduling algorithms are presented for both equal and unequal test length cases under the power constraint. The algorithms consist of three basic steps. First, we find a complete set of time compatible tests with power dissipation information associated with each test. Second, from these tests, we extract the lists of power compatible tests. And finally, we use a minimum cover table approach to find the optimal scheduling of the tests
Keywords :
built-in self test; graph theory; integrated circuit testing; logic testing; minimisation; resource allocation; scheduling; BIST control scheme; IC testing; NP complete problem; bipartite resource allocation graph; logic testing; minimum cover table approach; model-based formulation; optimum test scheduling algorithms; power compatible tests; power constraint scheduling; power dissipation information; search space reduction; test scheduling problem; time compatible tests; Circuit testing; Digital integrated circuits; Energy consumption; Integrated circuit testing; Optimal scheduling; Performance evaluation; Power dissipation; Resource management; Scheduling algorithm; System testing;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282700
