Design strategy for biquad-based continuous-time low-pass filters

This paper presents a design procedure for high-order continuous time low-pass filters based on the cascade of biquadratic cells. The proposed approach is amenable for integration, as it takes into account the maximum capacitance spread imposed by the available technology, and also allows a tradeoff between noise and maximum linear range to be met, thereby improving the dynamic range. Simulations both at system and transistor level are provided confirming the effectiveness of the procedure. Compared to the standard design approach of a 10-pole Gm-C filter and using a 65-nm CMOS process, the proposed approach achieves a noise reduction from 8.2 mV_rms to 4.9 mV_rms and a dynamic range improvement of 4.1dB. The paper is also useful as a tutorial for the effect of noise in multi-stage biquad filters.