VLSI architecture for HDTV motion estimation based on block-matching algorithm

A systolic array architecture based on an efficient data-flow management for implementing the full-search block-matching algorithm for HDTV motion estimation is described. It is capable of treating (16×16)-blocks, with a displacement of -8/+7 pixels. Serial data inputs save the pin counts and all the input data in current frame are read only once to keep the requirements to external units to a minimum. A simplified PE design reduces the computation to 1/3 of that by directly implementing the original algorithm without any influence on the performance. Simulation results show that pixel rates at about 150 MHz can be reached with 0.8 μm CMOS technology. Owing to the highly regular and modular properties, the proposed architecture is suitable for VLSI implementation. Transistor count is estimated about 320,000, which shows that the architecture can be realized in a single chip