Modeling And Performance Analysis of GALS architectures

In this paper we present a comparison of three clock control schemes and how it can be applied to an existing partitioned synchronous architecture to obtain a reliable, low latency and efficient globally asynchronous and locally synchronous architectures. The comparison highlights the advantages and disadvantages of one scheme over the other in terms of logical correctness, circuit implementation, performance and relative power consumption. We also present here circuit solutions for stretchable and data driven clocking schemes. These circuit solutions can be easily plugged into existing partitioned synchronous islands. To enable early evaluation of functional correctness, this paper proposes the use of Petri net modeling technique to model the asynchronous control blocks that constitute the interface between the synchronous islands