DocumentCode
1715324
Title
An improved deductive fault simulator
Author
Sureshkumar, P.R. ; Jacob, James ; Srinivas, M.K. ; Agrawal, Vishwani D.
Author_Institution
Hindustan Aeronaut. Ltd., Bangalore, India
fYear
1994
Firstpage
307
Lastpage
310
Abstract
We propose several improvements to the well known deductive fault simulation algorithm. First, sensitivity analysis is used during true value simulation to classify each gate of the circuit into one of the two classes, namely, definitely sensitive (DS) or potentially sensitive (PS). For these classes, simple rules are given to compute the output fault list from the input fault lists. Further, the basic operations of set union, set intersection and set difference, used in fault list computation, are made highly efficient by novel pointer referencing on implicitly ordered fault lists. Performance enhancements over the basic deductive fault simulation algorithm are demonstrated by experimental results on ISCAS-85 combinational benchmark circuits. Experimental results on ISCAS-89 sequential benchmarks show that our improvements make the simulator faster than a highly efficient concurrent fault simulator, Hysim-3
Keywords
circuit analysis computing; fault location; logic testing; sensitivity analysis; set theory; deductive fault simulation algorithm; deductive fault simulator; fault list computation; input fault lists; output fault list; pointer referencing; sensitivity analysis; set difference; set intersection; set union; true value simulation; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Jacobian matrices; Logic circuits; Logic gates; Sensitivity analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location
Calcutta
ISSN
1063-9667
Print_ISBN
0-8186-4990-9
Type
conf
DOI
10.1109/ICVD.1994.282708
Filename
282708
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