Development of a fast readout chip in deep submicron technology for pixel hybrid detectors

This paper presents a design and measurements of multichannel integrated circuits in 90 nm CMOS dedicated to readout of hybrid pixels detectors in imaging applications. The chip contains a matrix of 40 × 32 pixels with the size of 100μm × 100μm. Each pixel contains a charge sensitive amplifier, a main amplifier stage, two discriminators with trim DACs and two 16-bit ripple counters. The nominal power consumption per pixel is 42 μW. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 μV/e^- or 64 μV/e^- in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e^- rms and rises to 106 e^- rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to a 12 e^- rms at the input. A dead time in the front-end as low as 117 ns (paralyzable model) can be set. The chip can operate in the continuous readout mode and in readout mode separate from exposure. The ideas of building large area detector using through silicon via is also presented.