Hierarchical reconfiguration of VLSI/WSI arrays

Author

Bhatia, Dinesh ; Rajagopalan, Ramesh ; Katkoori, Srinivas

Author_Institution

Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA

fYear

1994

Firstpage

349

Lastpage

352

Abstract

We present a reconfiguration algorithm for yield enhancement of VLSI/WSI arrays. Our algorithm, is based on row/column elimination. We introduce the notion of element-bypass and use it to eliminate partial row(s) and partial column(s). In doing so we enhance the harvest greatly. Experimentally we are able to attain harvest which is many folds better than that reported in comparable studies. Our method has no hardware overhead and compares well with other methods that have substantial hardware overhead

Keywords

VLSI; circuit layout CAD; graph theory; network routing; VLSI/WSI arrays; element-bypass; gracefully degradable reconfiguration; harvest enhancement; hierarchical reconfiguration; partial column elimination; partial row elimination; reconfiguration algorithm; row/column elimination; weighted bipartite graph; yield enhancement; Circuit faults; Degradation; Hardware; Integrated circuit interconnections; Integrated circuit technology; Large-scale systems; Manufacturing processes; Silicon; Terminology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Conference_Location

Calcutta

ISSN

1063-9667

Print_ISBN

0-8186-4990-9

Type

conf

DOI

10.1109/ICVD.1994.282717

Filename

282717