Title :
Design and characterization of SiGe TFT devices and process using Stanford´s test chip design environment
Author :
Kumar, M.V. ; Subramanian, V. ; Saraswat, K.C. ; Plummer, J.D. ; Lukaszek, W.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
Stanford´s test chip environment has been used to rapidly prototype a SiGe TFT process. The environment selected test structures tailored for the device/process. Then, with minimal effort and using parameterized test structures, the designer assembled a diagnostic test module. This module was used successfully in the development and optimization of the process, leading to the fabrication or high performance SiGe TFTs
Keywords :
Ge-Si alloys; semiconductor device testing; semiconductor materials; semiconductor technology; thin film transistors; SiGe; SiGe TFT device; Stanford test chip design environment; diagnostic module; fabrication; process optimization; rapid prototyping; Chip scale packaging; Design optimization; Dielectric substrates; Doping; Germanium silicon alloys; Optical films; Prototypes; Silicon germanium; System testing; Thin film transistors;
Conference_Titel :
Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3243-1
DOI :
10.1109/ICMTS.1997.589363
