Title :
A stacked Cascode CMOS SOI power amplifier for mm-wave applications
Author :
Helmi, S.R. ; Jing-Hwa Chen ; Mohammadi, Soheil
Author_Institution :
Purdue Univ., West Lafayette, IN, USA
Abstract :
A millimeter-wave power amplifier (PA) implemented in a commercial 45nm CMOS SOI technology is presented. The PA design is based on stacking of two dynamically-biased Cascode transistor cells where drain-source voltages of individual transistors are added constructively to increase the output power. The PA output impedance is the sum of the output impedances of the two Cascode cells and is optimized to match to a 50 Ω load. At the operating frequency of 50 GHz and under a power supply of 4 V, the PA provides a saturated output power PSAT of 19 dBm (~80 mW), a -1dB output compression point (P1dB) of 16.3 dBm and a peak power-added efficiency (PAE) and drain efficiency (DE) of 28% and 40%, respectively.
Keywords :
CMOS integrated circuits; impedance matching; millimetre wave power amplifiers; silicon-on-insulator; CMOS SOI technology; PA output impedance; drain-source voltages; dynamically-biased cascode transistor cells; efficiency 28 percent; efficiency 40 percent; frequency 50 GHz; millimeter-wave power amplifier; resistance 50 ohm; size 45 nm; stacked cascode CMOS SOI power amplifier; voltage 4 V; CMOS integrated circuits; CMOS technology; Frequency measurement; Gain measurement; Q measurement; Thickness measurement; Topology; CMOS; Cascode; High Efficiency; Power Amplifier; SOI; Stacked Transistors;
Conference_Titel :
Microwave Symposium (IMS), 2014 IEEE MTT-S International
Conference_Location :
Tampa, FL
DOI :
10.1109/MWSYM.2014.6848589
