Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing

Author

Tripathy, Suryasnata ; Omprakash, L.B. ; Mandal, Sushanta K. ; Patro, B.S.

Author_Institution

KIIT Univ., Bhubaneswar, India

fYear

2015

Firstpage

1

Lastpage

6

Abstract

Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low power designs are realized in 45 nm CMOS Process technology using Cadence EDA tool.

Keywords

CMOS logic circuits; computer architecture; digital signal processing chips; low-power electronics; mathematics computing; multiplying circuits; performance evaluation; CMOS process technology; Cadence EDA tool; Urdhva Tiryakbhyam sutra; Vedic mathematics; digital signal processor; high speed computing; low power multiplier architectures; multiplier units; size 45 nm; word length 4 bit; word length 8 bit; Adders; Computer architecture; Delays; Logic gates; Power demand; Topology; Transistors; CMOS; High speed; Low power; Urdhva Tiryakbhyam; Vedic multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication, Information & Computing Technology (ICCICT), 2015 International Conference on

Conference_Location

Mumbai

Print_ISBN

978-1-4799-5521-3

Type

conf

DOI

10.1109/ICCICT.2015.7045662

Filename

7045662