• DocumentCode
    1716044
  • Title

    Simulated annealing with artificial neural network fitness function for ECG amplifier testing

  • Author

    Grzechca, Damian

  • Author_Institution
    Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
  • fYear
    2011
  • Firstpage
    49
  • Lastpage
    52
  • Abstract
    The paper presents new hybrid procedure for analog circuit fault clustering with the use of simulated annealing and self-organizing neural network. Main goal of the method is to find best PWL excitation under maximum diagnosability of the circuit. Optimization is done with simulated annealing. For each node in the optimization the goal function ranks how well a neural network performs in the classification of the circuit of interest. The testing procedure is performed in time domain and therefore simulated annealing optimizes piece wise linear (PWL) excitation. The neural network input data comes from the circuit test point(s). Self-organizing map (SOM) has been applied in order to cluster all circuit states into possible separate groups. So, it works as a feature selector and classifier. The procedure has been applied for ECG amplifier and then results have been evaluated. The hybrid approach shows good efficiency in reasonable time.
  • Keywords
    amplifiers; analogue circuits; circuit analysis computing; circuit testing; electrocardiography; fault diagnosis; feature extraction; pattern classification; pattern clustering; piecewise linear techniques; self-organising feature maps; simulated annealing; ECG amplifier testing; PWL excitation; analog circuit fault clustering; artificial neural network fitness function; circuit classification; circuit state clustering; circuit test point; feature selector; maximum circuit diagnosability; piece wise linear excitation; self-organizing map; self-organizing neural network; simulated annealing; Circuit faults; Correlation; Indium phosphide; Silicon; Simulated annealing; Testing; ECG amplifier; analog fault diagnosis; neural network; self organizing map; simulated annealing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuit Theory and Design (ECCTD), 2011 20th European Conference on
  • Conference_Location
    Linkoping
  • Print_ISBN
    978-1-4577-0617-2
  • Electronic_ISBN
    978-1-4577-0616-5
  • Type

    conf

  • DOI
    10.1109/ECCTD.2011.6043396
  • Filename
    6043396