Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model

Author

Consoli, Elio ; Giustolisi, Gianluca ; Palumbo, Gaetano

Author_Institution

Dipt. di Ing. Elettr., Elettron. ed Inf., Univ. degli Studi di Catania, Catania, Italy

fYear

2011

Firstpage

512

Lastpage

515

Abstract

In this paper, an ultra-compact I-V nanometer MOS model, suitable for the analysis of digital circuits, is first proposed. All the main physical effects are included through nine parameters and the model is shown to allow an accurate and quick estimation of DC transfer curves or SRAM noise margins.

Keywords

MOS digital integrated circuits; MOSFET; SRAM chips; invertors; nanoelectromechanical devices; DC transfer curve estimation; SRAM noise margin evaluation; digital circuit analysis; inverter transfer curve evaluation; ultracompact I-V nanometer MOS model; Integrated circuit modeling; Inverters; MOS devices; MOSFET circuits; Noise; Random access memory; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design (ECCTD), 2011 20th European Conference on

Conference_Location

Linkoping

Print_ISBN

978-1-4577-0617-2

Electronic_ISBN

978-1-4577-0616-5

Type

conf

DOI

10.1109/ECCTD.2011.6043401

Filename

6043401

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1716277