Impact of NMOS/PMOS imbalance in Ultra-Low Voltage CMOS standard cells

In this paper, the impact of the NMOS/PMOS imbalance on Ultra-Low Voltage (ULV) circuits and their design is discussed within a unitary framework for the first time. Variations are shown to dramatically affect imbalance due to the long-tailed probability density and high variability. The impact of the imbalance on the minimum supply voltage V_DD,min ensuring correct gate switching is studied analytically. The results theoretically justify the experimental results in [1], which agree very well with the predictions. The impact of the imbalance on the leakage energy in VLSI systems is also analyzed through a simple but representative example. An analytical model is presented to predict such leakage energy increase due to imbalance. Extensive results in 65-nm CMOS are shown to agree with the design considerations and quantitative models presented.