DocumentCode :
1716463
Title :
Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution
Author :
Mason, Jack L. ; Simco, Gregory E.
Author_Institution :
Grad. Sch. of Comput. & Inf. Sci., Nova Southeastern Univ., Fort Lauderdale, FL, USA
fYear :
2013
Firstpage :
74
Lastpage :
76
Abstract :
Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.
Keywords :
digital simulation; multi-threading; parallel processing; program testing; software architecture; architectural deficiencies; architecture validation; context-preserving proposal; microarchitecture enhancement validation; simulation overhead; target environment simulation; thread-level speculation proposals; thread-level speculative execution; Computer architecture; Instruction sets; Microprocessors; Proposals; Synchronization; Testing; speculative execution; validation testing; system simulation; target environment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microprocessor Test and Verification (MTV), 2013 14th International Workshop on
Conference_Location :
Austin, TX
ISSN :
1550-4093
Type :
conf
DOI :
10.1109/MTV.2013.27
Filename :
6926105
Link To Document :
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