Title :
Hardware implementation of lifting based wavelet transform
Author :
Gholipour, Morteza ; Noubari, Hossein Ahmadi
Author_Institution :
Behshahr Branch, Islamic Azad Univ., Behshahr, Iran
Abstract :
In this paper, a VLSI implementation of the lifting-based Discrete Wavelet Transform (DWT) is presented. The behavioral description of integer-to-integer CDF (2,2) lifting wavelet, which is used in image compression has been coded in Verilog Hardware Description Language (HDL). The code has been synthesized and then implemented using both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) design approaches. Post-synthesis and post-layout simulations verify the appropriate operation of he architecture. The resulting hardware can be used in image compression applications such as JPEG2000.
Keywords :
VLSI; application specific integrated circuits; data compression; field programmable gate arrays; image coding; wavelet transforms; FPGA; JPEG2000; VLSI implementation; Verilog Hardware Description Language; application specific integrated circuit design; behavioral description; field programmable gate array design; hardware implementation; image compression applications; integer-to-integer CDF (2,2) lifting wavelet; lifting based wavelet transform; post-layout simulation; post-synthesis simulation; Discrete wavelet transforms; Filter bank; Image coding; Integrated circuit modeling; Multiresolution analysis; FPGA; Lifting Scheme; VLSI; Wavelet;
Conference_Titel :
Signal Processing Systems (ICSPS), 2010 2nd International Conference on
Conference_Location :
Dalian
Print_ISBN :
978-1-4244-6892-8
Electronic_ISBN :
978-1-4244-6893-5
DOI :
10.1109/ICSPS.2010.5555571
