Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator

We present the design of an iSCSI hardware accelerator for the initiator subsystem of a host bus adapter (iSCSI HBA). By analyzing the UNH-iSCSI open source code, first we evaluate the software performance and present a general methodology that transforms the software C code into the hardware HDL implementation. For the hardware module, the datapath design maximizes the concurrent accesses achievable within a clock cycle by using a dual-port descriptor memory. The synthesizable iSCSI hardware accelerator achieves 100 MHz speed and costs about 85K gates in the 0.18u technology. The design is able to meet the requirement of 1Gbps network when the average iSCSI PDU size is greater than 125 bytes