DocumentCode :
1717346
Title :
A low-power fully differential 9-bit C-2C cyclic ADC
Author :
Bako, Niko ; Baric, Adrijan
Author_Institution :
Univ. of Zagreb, Zagreb, Croatia
fYear :
2011
Firstpage :
576
Lastpage :
579
Abstract :
This paper describes a low-power fully differential cyclic ADC. It utilizes a 3-bit C-2C ladder to achieve 9-bit resolution. For the 9-bit resolution the 3-bit C-2C ladder occupies 64 times less area than a binary weighted capacitance array. The operational amplifier with the slew rate detection is used in order to increase the speed of the ADC. The simulated power consumption of the ADC is 33 μW@3.3 V at the sampling rate of 10 kS/s. The DNL and INL are both less than 0.53 LSB. The spurious-free dynamic range (SFDR) is 63 dB and the signal-to-noise and distortion ratio (SNDR) is 54.2 dB. The equivalent number of bits (ENOB) is 8.7.
Keywords :
analogue-digital conversion; low-power electronics; operational amplifiers; C-2C ladder; binary weighted capacitance array; low-power fully differential cyclic ADC; operational amplifier; power 33 muW; slew rate detection; spurious-free dynamic range; voltage 3.3 V; word length 3 bit; word length 9 bit; Arrays; Capacitance; Capacitors; Operational amplifiers; Power demand; Radiofrequency identification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuit Theory and Design (ECCTD), 2011 20th European Conference on
Conference_Location :
Linkoping
Print_ISBN :
978-1-4577-0617-2
Electronic_ISBN :
978-1-4577-0616-5
Type :
conf
DOI :
10.1109/ECCTD.2011.6043599
Filename :
6043599
Link To Document :
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