High performance Haar Wavelet transform architecture

This paper proposes high performance dedicated hardware architecture for the Haar Wavelet transform, whose structure is based on nine levels of decomposition. The architecture is described in hardware description language VHDL, and it has been designed by using fixed point arithmetic, and also using efficient arithmetic operators into their sub modules. The efficiency of the architecture was proved by showing that the error from both the signals of the architecture and the signals from a reference model, described in float point in the MATLAB^® environment, is negligible. Moreover, the synthesis results clearly show the higher performance of the proposed architecture over other solutions from the literature, where gains in terms of frequency operation and area utilization are reported.