Title :
A fully automated large-scale addressable test chip design with high reliability
Author :
Zhang, Bo ; Pan, Weiwei ; Zheng, Yongjun ; Shi, Zheng ; Yan, Xiaolang
Author_Institution :
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
Abstract :
During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper, we present a novel large-scale addressable test chip development procedure. Based on components for automation, this procedure is fully integrated and able to reduce layout time to 10% and eliminate much of the potential for human error. A 32×32 array on a 45nm technology has been designed and manufactured with this procedure; the silicon test data further prove the reliability and effectiveness of this procedure.
Keywords :
electronic design automation; integrated circuit layout; integrated circuit reliability; integrated circuit testing; addressable method; chip area; fully automated large scale addressable test chip design; large scale addressable test chip development; modern semiconductor process; Arrays; Chip scale packaging; Integrated circuit modeling; Layout; Reliability engineering; Routing; addressable; automated; design reliability; test chip; yield;
Conference_Titel :
Circuit Theory and Design (ECCTD), 2011 20th European Conference on
Conference_Location :
Linkoping
Print_ISBN :
978-1-4577-0617-2
Electronic_ISBN :
978-1-4577-0616-5
DOI :
10.1109/ECCTD.2011.6043609
