The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor

Author

Burgess, B. ; Alexander, M. ; Ying-Wai Ho ; Litch, S.P. ; Mallick, Shankhanaad ; Ogden, D. ; Sung-Ho Park ; Slaton, J.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1994

Firstpage

300

Lastpage

306

Abstract

The PowerPC 603 microprocessor is the second member of the PowerPC microprocessor family. The 603 is a superscalar implementation featuring low power operation of less than 3 watts while maintaining high performance of 75 SPECint92 (estimated) at 80 MHz. The 7.4 mm by 11.5 mm design is implemented in 0.5 /spl mu/m, four-level metal CMOS technology. The 603 features dual 8-kByte instruction and data caches and a 32/64-bit system bus. Peak instruction rates of 3 instructions per clock cycle give outstanding performance to notebook and portable applications.<>

Keywords

CMOS integrated circuits; IBM computers; microprocessor chips; portable computers; reduced instruction set computing; 0.5 micron; 11.5 mm; 3 W; 32 bit; 32/64-bit system bus; 64 bit; 7.4 mm; 8 kbyte; 80 MHz; PowerPC 603 microprocessor; data caches; four-level metal CMOS technology; high performance; instruction caches; low power operation; notebook computers; peak instruction rates; portable computers; superscalar RISC microprocessor; CMOS technology; Clocks; Computer architecture; Decoding; Microprocessors; Pipelines; Power dissipation; Reduced instruction set computing; System buses; Trademarks;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '94, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-5380-9

Type

conf

DOI

10.1109/CMPCON.1994.282895

Filename

282895