Title :
POWER2: performance measurement and analysis of TPC-C
Author :
Franklin, M.T. ; Welbon, E.H.
Author_Institution :
IBM Corp., Austin, TX, USA
Abstract :
This paper discusses the implementation and features of the POWER2 system´s embedded hardware performance monitor, describes its application to the analysis of the behavior of the Transaction Processing Performance Council´s TPC-C benchmark on the POWER2 CPU, simulating an on-line transaction processing (OLTP) workload, and summarizes the results of the analysis. The POWER2 performance monitor provides hardware measures that are important to software developers tuning the operating system and application software, as well as to system designers responsible for the development of new systems. The measures characterize storage system performance and compiler instruction scheduling opportunity, both critical to good system performance.<>
Keywords :
IBM computers; microprocessor chips; performance evaluation; POWER2 CPU; TPC-C benchmark; Transaction Processing Performance Council; application software tuning; compiler instruction scheduling; embedded hardware performance monitor; online transaction processing workload; operating system tuning; storage system performance; systems development; Counting circuits; Hardware; Monitoring; Performance analysis; Reduced instruction set computing; Registers; Semiconductor device measurement; Software measurement; Software performance; Yarn;
Conference_Titel :
Compcon Spring '94, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-5380-9
DOI :
10.1109/CMPCON.1994.282900
