DocumentCode
1718277
Title
POWER2: architecture and performance
Author
White, S.W.
Author_Institution
IBM Corp., Austin, TX, USA
fYear
1994
Firstpage
384
Lastpage
388
Abstract
A dichotomy exists among the various approaches to achieving performance in the workstation and server markets. Some implementations aggressively pursue high clock rate goals, often by settling for less instruction-level parallelism. In contrast, IBM workstations have been well-known for supporting high degrees of concurrency. POWER2 (Performance Optimized With Enhanced RISC) based RISC System/6000 workstations further widen the gap between the instruction-level parallelism and clock rate approaches. This paper describes the architecture and performance aspects of these new systems.<>
Keywords
IBM computers; clocks; parallel architectures; parallel machines; performance evaluation; reduced instruction set computing; workstations; IBM workstations; POWER2; Performance Optimized With Enhanced RISC; RISC System/6000 workstations; clock rate; computer architecture; concurrency; instruction-level parallelism; performance; servers; Bandwidth; Clocks; Computer architecture; Concurrent computing; Functional programming; Monitoring; Parallel processing; Reduced instruction set computing; Testing; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '94, Digest of Papers.
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-5380-9
Type
conf
DOI
10.1109/CMPCON.1994.282902
Filename
282902
Link To Document