Title :
PA7200: a PA-RISC processor with integrated high performance MP bus interface
Author :
Kurpanek, G. ; Chan, K. ; Zheng, J. ; Delano, E. ; Bryg, W.
Abstract :
A new processor implementing Hewlett-Packard´s PA-RISC 1.1 (Precision Architecture) has been designed. This latest design incorporates many improvements over the HP PA7100 CPU, including increased frequency, instruction and data cache prefetching, enhanced superscalar execution, and enhanced multiprocessor support. The PA7200 connects directly to a new split transaction, 120 MHz, 64-bit bus capable of supporting multiple processors and multiple outstanding memory reads per processor. A novel fully associative on-chip data cache, which is accessed in parallel with an external data cache, is used to reduce the miss rate and facilitate hardware and software directed prefetching to reduce average memory access time.<>
Keywords :
Hewlett Packard computers; buffer storage; microprocessor chips; multiprocessing systems; reduced instruction set computing; system buses; 120 MHz; 64 bit; HP PA7200 CPU; PA-RISC 1.1 processor; Precision Architecture; average memory access time; data cache prefetching; external data cache; fully associative on-chip data cache; hardware directed prefetching; instruction prefetching; integrated high performance multiprocessor bus interface; miss rate; multiple outstanding memory reads; parallel access; software directed prefetching; split transaction bus; superscalar execution; CMOS technology; FETs; Frequency; Hardware; Pipelines; Prefetching; Process design; Reduced instruction set computing; System performance; Workstations;
Conference_Titel :
Compcon Spring '94, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-5380-9
DOI :
10.1109/CMPCON.1994.282903
