The PowerPC 603 C++ Verilog interface model

Describes an object-oriented model of the PowerPC 603 microprocessor, and the incorporation of this model into Verilog using the Programming Language Interface (PLI). The model is behavioral and written in C++. It has a stand-alone mode with an external environment simulated in C++. In the Verilog mode, this external environment is disabled and would be simulated in Verilog. This paper discusses the stand-alone model, the procedural interface used to communicate with the external world, and the implementation of the Verilog PLI interface. It also discusses uses of the models in the two modes.<>