DocumentCode
171851
Title
Time models of dynamic and static reconfiguration in FPGAs
Author
Kondelova, Anna ; Cuntala, Jozef
Author_Institution
Dept. of Mechatron. & Electron., Univ. of Zilina, Zilina, Slovakia
fYear
2014
fDate
19-20 May 2014
Firstpage
451
Lastpage
454
Abstract
This paper is dealing with ways of configuration of the FPGA devices and time parameters of various types of configurations. Time model of configurations and reconfigurations has been designed. Outputs of the designed model are times of configurations, reconfigurations and partial reconfiguration derived from technical parameters of devices and from length of bitstreams.
Keywords
field programmable gate arrays; logic design; FPGA devices; dynamic reconfiguration; partial reconfiguration; static reconfiguration; time models; Decoding; Field programmable gate arrays; PROM; Process control; Random access memory; Registers; FPGA; bitstream; dynamic reconfiguration; static configuration;
fLanguage
English
Publisher
ieee
Conference_Titel
ELEKTRO, 2014
Conference_Location
Rajecke Teplice
Print_ISBN
978-1-4799-3720-2
Type
conf
DOI
10.1109/ELEKTRO.2014.6848936
Filename
6848936
Link To Document